A flash memory device has the advantages of erasable programmable read-only memory (EPROM), capable of performing programming and erasing operations, and electrically erasable programmable read-only memory (EEPROM), capable of electrically performing programming and erasing operations. Flash memory devices can realize storage of one bit per transistor, and can electrically program and erase data.
Flash memory is non-volatile, with a laminate structure including a floating gate and a control gate. The floating gate and a control gate are laminated in the form of a conductive polysilicon double-layer over a tunnel oxide film. In a flash memory device, an oxide-nitride-oxide (ONO) structure, acting as an interlayer capacitor dielectric, is interposed between the floating gate and the control gate. A bias is applied from the control gate through the ONO layer to the floating gate depending on coupling ratio. Programming and erasing are controlled by a higher bias.
Hereinafter, a related flash memory device will be described in brief. A first polysilicon layer for a floating gate, an ONO interlayer dielectric, a second polysilicon layer for a control gate and a hard mask film are sequentially deposited over a semiconductor substrate and the resulting structure is etched using a hard mask film pattern to form a gate electrode. Then, high-temperature oxide (HTO) is formed over the entire surface of the semiconductor substrate including the gate electrode. A sidewall nitride film and a sidewall oxide film are sequentially deposited over the HTO. The resulting structure is etched to form an oxide/nitride/oxide (ONO) spacer.
Then, sidewall barrier oxide and sidewall barrier nitride (SBN) are formed as barrier films over the entire surface of the semiconductor substrate including the gate electrode. The sidewall barrier oxide and sidewall barrier nitride present over the gate electrode are removed by dry etching for the subsequent process, i.e., salicide treatment. Then, sidewall barrier oxide and sidewall barrier nitride remaining over the sidewall of the gate electrode are removed by wet etching.
However, this method for manufacturing a related flash memory device requires thermal treatment of sidewall barrier oxide and sidewall barrier nitride at high temperatures, like a process for depositing a hard mask film requiring thermal treatment at high temperatures, thus increasing thermal treatment and significantly increasing the thermal budget. This exposure to heat causes a decrease of the channel between the source and drain and thus increases the probability of leakage current due to shorting.
Also, the general method requires simultaneous removal of sidewall barrier oxide and sidewall harrier nitride by wet etching. This has the disadvantages of adding to the overall process and causing undercut during wet etching.